Firmware Release 1565
=====================

LK, 22. November 2018

BUG: Debouncing PLL phase error in order to NOT react to the first phase error who could be caused by an 
     failure of the ethernet (bit error rate)
CHG: Send permanently errors when ethernet gap duration is saturated. this helps to recognize an open ring.




Firmware Release 1563
=====================

LK, 12. November 2018

CHG: Master and Slave Serializer with the same CRC calculation
CHG: Reverted empty packets back to zero content



Firmware Release 1561
=====================

LK, 5. November 2018

NEW: pLL plot signals using encoder phase A and B

     encoder device, Address 0x40 [19:16]
       0x0 => uncalibrated encoder phase A
       0x1 => calibrated encoder phase B
       0x2 => encoder phase A offset C1
       0x3 => encoder phase A amplitude A11
       0x4 => encoder phase A cross-amplitude A12
       0x8 => pll phase error
       0x9 => pll phase count of ring 1
       0xA => ethernet intermediate gap length of ring 1
       0xB => ethernet frame length of ring 1

     encoder device, Address 0x40 [23:20]
       0x0 => uncalibrated encoder phase B
       0x1 => calibrated encoder phase A
       0x2 => encoder phase B offset C2
       0x3 => encoder phase B amplitude A22
       0x4 => encoder phase B cross-amplitude A21
       0x8 => pll frequency
       0x9 => pll phase count of ring 2
       0xA => ethernet intermediate gap length of ring 2
       0xB => ethernet frame length of ring 2

CHG: ethernet frame tolerance set to +/-160ns
CHG: ethernet gap tolerance set to +/-320ns
CHG: timestamp crc error counted as a packet crc error
CHG: frame error, gap error and crc error of packets counted once every 100us
CHG: physical link device, see local bus description

FIX: pll not locked error when one timestamp with crc error occurs. this throws an error
     to the drive stopping the motion. Changed to pll not locked error when multiple 
     timestamp with crc error occurs. "multiple" is programmable from 1 to 128 with 
     default of 32.

FIX: crc calculation of ethernet rx and tx divided into two calculation steps to avoid
     wrong crc calculation when fpga device gets hot.


Firmware Release 1544
=====================

LK, 9. April 2018

FIX: PLL Locked threshold level changed from -64...63 to -512...511 due
     to problems with thermal caused frequency jumps. these jumps leaded
     to a trialink unlocked state throwing an error. The new threshold value 
     is a going back to the threshold of FW1302.



Firmware Release 1542
=====================

LK, 12. September 2017

NEW: Trialink Master Oscillator
     - pci bus 0x1018 : ieee-1588 nanoseconds rtc 
                        [31:0] RO 0-999'999'999 ns
               0x101C : ieee-1588 seconds rtc 
                        [31:0] RO seconds counter
               0x1020 : trialink oscillator
                        [15: 0] RW oscillator frequency +/- 200ppm
                        [31:16] RW pll delay in 10ns steps
NEW: Sigma-Delta 2nd order replaced by 1st order




Firmware Release 1537
=====================

LK, 2. July 2017

FIX: earth short detection with shorter pulse duration due to problems
     with rotor movements inducing voltage. long pulses are suitable to detect
     earth shorts over an inductance. Since this error is not damaging the drive
     this short test will be ommited. New drive generations will have three phase 
     measurements instead of two and the problem of the induced voltage can be 
     solved by summing all three phase currents which cancels out currents caused
     by the rotor movement.



Firmware Release 1532
=====================

LK, 27. April 2017

NEW: cyclic data with two pages for TSC / TSC3
     -> higher bridge voltage resolution



Firmware Release 1529
=====================

LK, 20. February 2017

NEW: rearranging pwm structure and signal flow
NEW: pwm short detection (phase-to-phase and phase-to-earth) for TS150, TS350 and TSP700
NEW: service device registers (device 0x01
     0x000000 RO [15: 0] : actual duration from receiving data to the begin of the 100kHz cycle
     0x000001 RO [15: 0] : minimum duration value, cleared by reading the register
     0x000001 RO [31:16] : maximum duration value, cleared by reading the register
FIX: refactoring Endat Receive (problems with the synthesis of the counters)
FIX: applying timing constraints for CDC instances

Although the pwm short detection is completed, it can't be used due to a missing drive enable delay.
During the short detection the pwm output is unusable for at least 2ms. Enabling when detecting the short
would lead to an current controller error because of no (wrong) current flow.  



Firmware Release 1494
=====================

LK, 7. December 2016

Trialink adapter release.

Bug Fix: table feeder device not recognized due to wrong local bus timeout behaviour.



Firmware Release 1475
=====================

LK, 8. January 2016


Branch based on release 1473.
Temporary bugfix until hardware replacement TOAI1 -> TOA1 and TOEA2 -> TOF1 takes place. 

LVDS interface of the option modules (TOAI1, TOEA2) modified in such a way that they work together with the permanently calibrating LVDS interfaces of the newest option module master (TSD80, MCI42).

CAUTION: Only direction option module to option module master works.



Firmware Release 1474
=====================

LK, 8. January 2016


Refactorings:
- Design separation between Artix7 and Spartan3e/Spartan6 (different tools)


Bug Fixes
- encoder amplitude error: reproting only when analog encoder used
- artix-7 distributed memory was only 16 bit intead of 32 bit wide



Firmware Release 1471
=====================

LK, 27. October 2015

1) new hardware type TOAI1 HR1
2) new hardware type TOEA1 HR1
3) new hardware type TOEA2 HR1 Analog 
4) new hardware type TOEA2 HR1 FFT
5) TSD80 with 20MHz current sampling and new filter
6) sending latched STO signals to DSP 
7) TSD80 with dual encoder support


Refactorings:
- Xilinx build process with XST and PlanAhead support
  - removal of configurations
  - different architectures changed to different components
  - avoiding assignments of vectors with different low and high indices
  - avoiding record field attributes e.g. data.x'length
  - removing assert in synthesizable code
  - avoiding identical component names from different libraries
  - avoiding equal names after record field substitution
    e.g. data.x will be the same as data_x
  - avoiding loops with bidirectional signals (e.g. mdio)
- Cdc and Sync library
- Firmware Id in a separate top level file
- Option Module port data types
- Monitor_IO Serializer with simpler reset logic (timing problems)
- Option Module in general
- Original and modified PciE code with same interface
- Eim Interface, adding debug utilities
- Fifo Interface
- Creating extended local bus library
- Removing TSD80 local bus interface

Bug Fixes
- Analog encoder logging swapped x and y
- TSD80 and MCI42 leds
- PWM local bus device did nor reflect the state of the STO signals
- PLL locked problems



Firmware Release 1395
=====================

LK, 26. Juni 2015

1) New hardware type TLOC100 HR3
2) New hardware type TLC100  HR3
3) New hardware type TL100   HR3
4) New hardware type MCI42   HR0
5) Analog encoder amplitude error bugfix
6) Monitors woth abo send
7) Pwm spread spectrum and soft switch on removed
8) Option module support
9) Complete pll refactoring with XCO-support


Refactorings:
- Clock domain crossing
- Data types
- Counters
- Memories
- Fifos
- Local Bus
- Current converter
- Phases a+c to u+v+w
- Monitors
- 3-wire and 4-wire spi 



Firmware Release 1306
=====================

LK, 25.10.2014
 
1) TSD80 Monitors with bidirectional abo's
2) extio with pull up instead of pull down


Firmware Release 1302
=====================

LK, 09.10.2014
 
1) Pwm soft turn off feature removed due to drive damage when using STO.



Firmware Release 1300
=====================

LK, 06.10.2014
do not use
 
1) Fifo starts with fifo empty state when one side is resetted.



Firmware Release 1299
=====================

LK, 24.09.2014
do not use
 
1) New common types library
2) Current converter with programmable sampling
3) Pwm spread spectrum removed due to an error inside the timing unit
4) STO signals driving directly shutdown
5) Rework clock domain crossing
6) Rework trialink fifos
7) rework table feeder
8) new AD80066 analog encoder interface
9) TSD80 support with ARM interface
A) PWM value register bugfix (update not working)
B) pci bus based sync trigger removed (registers 0x1200-0x1204)



Firmware Release 1283
=====================

LK, 03.04.2014
Use only for TS and TIOB devices
 
1) TS Rev. D integrated
2) TL300 and TLO300 
   - PciE Dma first implementation, only recommended for test purposes
   - DMA not yet stable
   - PciE with interrupts not yet stable
3) Analog Encoder with amplitude error signal
4) Endat FPGA Sythesis improvements
5) new analog output interpolation filter (TIOB, TADDAC)
6) PWM spread spectrum to improve EMC emmision



Firmware Release 1243
=====================

LK, 30.04.2013
 
1) TLC100 reset behaviour bugfix
2) Adding ready lead to the TLC100 device 



Firmware Release 1240
=====================

LK, 30.04.2013
 
1) TAD4 supportAdr 
   0x30 (3:2) : config register
   "00" -> phase signals sent by cyclic data (default)
   "01" -> unfiltered dig enc 1 sent by cyclic data
   "10" -> tad4 instead of phase A
   "11" -> reserved
2) PulseTrain_Single blockdiagram converted to vhdl code due to a ALDEC bug
3) New reset behaviour of the fifos
4) Trialink router: broadcast to broadcast skip
5) Trialink Status/Control bugfix (Unresolved timeout)



Firmware Release 1198
=====================

LK, 08.04.2013

do not use

 
1)  new hardware type TLO300 (PciE trialink master with USB observer)
2)  new PciE library from Xilinx
3)  refactoring of the table feeder (thread safe control and status signals)
4)  refactoring of the encoder analog signal logger with more memory and trigger 



Firmware Release 1189
=====================

LK, 06.02.2013

do not use

 
1)  TL300 SPI booting with 4 lanes
2)  removing encoder device with 4 filter edge frequencies feature 
    from release 1073 due to ressource saving
3)  removing current device with 4 filter edge frequencies feature 
    from release 1073 due to ressource saving
4)  obsolete ellipse registers converted to readback registers due to 
    software compatibility
5)  disabling service device due to ressource saving
6)  monitor commmunication with 32 bit crc calculation and automatic
    detection of the communication mode
7)  TL300 Rev. 0 release, TL300 Rev. Z not further supported



Firmware Release 1180
=====================

LK, 06.02.2013

do not use

 
1)  new hardware type TLO100 (Pci trialink master with USB observer)
    fully working





Firmware Release 1173
=====================

LK, 06.02.2013

do not use
 
1)  new hardware type TLO100 (PCI trialink master with USB observer)
    the USB observer is not yet running!
2)  refactoring of the trialink fifos and router
3)  encoder device with 4 filter edge frequencies
4)  current device with 4 filter edge frequencies
5)  removing programmable fifo size feature (PCI Adr 0x1008)





Firmware Release 1170
=====================

LK, 21.11.2012
 
1)  refactoring of encoder autocalib
2)  removal of old style encoder calibration using registers 0x68-0x6b of the 
    local bus encoder device.
3)  new features local bus encoder device:
    a) analog encoder latching with selectable index marker source
       Adr 0x44  
    b) digital encoder latching with selectable index marker source
       Adr 0x45
    c) analog encoder fast phase signal logging
       Adr 0x40 
       Adr 0x40 (25:25) : '0' -> logging trigger disabled (default)
                          '1' -> activate a/b signal logging
       Adr 0x40 (26:26)   '0' -> logging not active or not complete
                          '1' -> logging completed
       Adr 0x1000-0x11FF (15: 0)  : phase A signal logger memory
       Adr 0x1000-0x11FF (31: 16) : phase B signal logger memory
4)  refactoring of the encoder position filter
5)  refactoring of the digital in/out routing
    -> from multi-dimensional array to single dimension array (problems with Aldec)
6)  position filter device with multiple filter selection
    RW Adr 0x0000 (1:0) : filter select
                          "00" select filter 0, 3rd order Butterworth, 6.75kHz (default)
                          "01" select filter 1, 3rd order Butterworth, 9.80kHz
                          "10" select filter 2, 3rd order Butterworth, 12.7kHz
                          "11" select filter 3, 6rd order Butterworth, 19.0kHz
    RW Adr 0x8000-83FF (17 downto 0) : filter 0 coefficients
    RW Adr 0x8400-87FF (17 downto 0) : filter 1 coefficients
    RW Adr 0x8800-8BFF (17 downto 0) : filter 2 coefficients
    RW Adr 0x8C00-8FFF (17 downto 0) : filter 3 coefficients
7)  current filter device with multiple filter selection
    RW Adr 0x0000 (1:0) : filter select
                          "00" select filter 0, 3rd order Butterworth, 13.7kHz (default)
                          "01" select filter 1, 3rd order Butterworth, 19.6kHz
                          "10" select filter 2, 3rd order Butterworth, 25.5kHz
                          "11" select filter 3, 6rd order Butterworth, 39.0kHz
    RW Adr 0x8000-83FF (17 downto 0) : filter 0 coefficients
    RW Adr 0x8400-87FF (17 downto 0) : filter 1 coefficients
    RW Adr 0x8800-8BFF (17 downto 0) : filter 2 coefficients
    RW Adr 0x8C00-8FFF (17 downto 0) : filter 3 coefficients
8)  refactoring of the current filter   
9)  pwm soft turn off time reduced from 10us to 1us
10) memory din / dout convention adapted to xilinx standard
11) pci interface : sync delay counter enabled
12) time stamp starts at 0xFE001F00
    this leads to the first wrap after 335s. the next wrap will be 12h later.
13) the pci interface time stamp update rate changed from 100us to 10us.




Firmware Release 1159
=====================

LK, 02.07.2012

1) TSP700 center control error level incresed from 36V to 72V
2) Encoder analog filter configurable by encoder local bus register 0x43.
   Default is 0xC, can be set to 0x9 or 0xA to increase the encoder counting
   frequency up to 600kHz.
   Adr 0x43 (3: 0) : encoder phase signal filter configuration
                     "0000" -> bypass
                     "0001" -> Gauss 0.75 filter (fastest Gauss)
                     "0010" -> Gauss 1.00 filter
                     "0011" -> Gauss 1.25 filter
                     "0100" -> Gauss 1.50 filter
                     "0101" -> Gauss 2.00 filter
                     "0110" -> Gauss 3.00 filter (slowest Gauss)
                     "0111" -> Sinc 3 filter (fastest Sinc)
                     "1000" -> Sinc 4 filter
                     "1001" -> Sinc 5 filter
                     "1010" -> Sinc 6 filter
                     "1011" -> Sinc 8 filter
                     "1100" -> Sinc 10 filter (slowest Sinc) -> default
                     "1101" -> Cic 2 filter (fastest Cic)
                     "1110" -> Cic 5 filter
                     "1111" -> Cic 8 filter (slowest Cic)




Firmware Release 1156
=====================

LK, 13.06.2012

1) New board TL300 (PciE trialink adapter)
2) Init values for the programmable delay line and the sync reset
3) Better hardware revision support
4) Memories changed to write first (due to spartan6 compatibility)
5) Complete center control rework
6) Programmable pwm signal shift to avoid control limit cycles
7) physicals evaluated with clock distribution nets (spartan6) 
8) STO support




Firmware Release 1127
=====================

LK, 16.03.2012

1) Trialink bit error generator for debug purposes
2) Center control for 3 level devices
3) Pwm gap bugfix (short cuts at high output voltages)
4) New device TSP350 (400V @ 20A)
5) TSP350 and TSP700 overcurrent debounce time is 3us




Firmware Release 1089
=====================

LK, 18.11.2011

Bug fix release

1) DigitalIn Processing bugfix.
   Digin Debounce time resolution is 10us.
   Default Debounce time is 40us.




Firmware Release 1088
=====================

LK, 25.10.2011

Bug fix release
DO NOT USE!

1) DigitalIn Processing changed
   due to FPGA timing problems.
   No functional change!




Firmware Release 1087
=====================

LK, 11.10.2011

Bug fix release

1) Avnet Board with encoder DDS Test environment
2) HRID input not further in use -> removed
3) Spartan6 support for new designs
4) TC1, TC2, TSP700_HR1 implementation
5) High Speed Encoder implementation (mixing analog and digital counting)
6) Autocalib with minimum radius
7) trialink router: unused connection removal
8) new ethernet mii interface with better timing and "55" handling
9) trialink sync pll change rate limited to 10
10) TSC with pullups on portAin
11) TSC with 3us overcurrent debounce time




Firmware Release 1072
=====================

LK, 12.05.2011

Bug fix release

1) Trialink timing improvement solves communication problems of the TLC100




Firmware Release 1055
=====================

LK, 08.05.2011

Bug fix release

1) Monitor IO Device:
   - More diagnostic features with new diagnostics memory map.
   - Ignoring zero packets
   - Ignoring packet after crc error

2) Ethernet periphery will be resetted only at bootup (TL100, TLC201, TLC100)
   (not every time when the trialink gets identified)

3) The Trialik adapter (TL100, TLC201, TLC100) will be kept at reset for 5 seconds 
   after booting the PC




Firmware Release 1049
=====================

LK, 03.05.2011

Bug fix release

1) Ready led on TSP700 did not work properly




Firmware Release 1048
=====================

LK, 21.04.2011

release for interbal use only
no functional change

1) config library removed due to naming conflict when using xilinx sythesis xst

2) renaming tiob1 to tiob01 and tiob2 to tiob02



Firmware Release 1047
=====================

LK, 19.04.2011

Bug fix release

1) TLC100 Bug fix
   - better "55" ethernet preamble detection
   - clocking the slave trialink macro while the master macro is in reset state

2) SPI (local bus device) timing improvement by an additional pipeline state

3) Endat timing improvement by changing from one process to two process state machine representation

4) Monitor watchdog and crc bug fix (crc not evaluated)
   - disconnecting the Save Torque Off connector ended in a temperature error condition
     due to the missing watchdog and crc



Firmware Release 1041
=====================

LK, 21.03.2011

Production Release


1) Point table controller additionally connected to the pci bus.
   The memory range is 0x5000-0x57FC
   The memory map equals to the memory mmap of the point table device
   when multiplying the address by 4.
2) Point table controller allows a reload of the enable register when
   wrapping in the cyclic mode.



Firmware Release 1038
=====================

LK, 11.03.2011

Production Release


1) New PWM unit (2- and 3-level pwm)
   This Firmware works with DSP FWID>=1024 only !!
2) Monitor interface with CRC protection



Firmware Release 744
====================

LK, 19.10.2010

Production Release

1) Monitog data protected with a watchdog.
2) High speed analog encoder with evaluation of digital encoder signal
   (supplied by extio or digital encoder 1).
   Feature can be used by setting encoder device adr 0x40 bit 2.  
   --> feature not yet released
3) TIOB1 with different defaults than TS. This fixes the Endat default value
   problem.
4) Complete rework of the Monitor_IO device (including cyclic data exchange)
5) New device number 0x202 for TLC100 cards to omit problems with the TLC201 device.




Firmware Release 730
====================

LK, 19.07.2010

Bug fix release

1) Based on release 728
2) Endat changed to backward compatibility
   -> endat hardware initialized by default
   -> do not use woth TIOB's !!!




Firmware Release 729
====================

LK, 19.07.2010

Debug Release

1) Trialink locked set to '1', this omits
   a software error message when using 
   the drive in standalone mode and with modulo move.




Firmware Release 728
====================

LK, 19.07.2010

Production Release

1) New SPI device (STM32 based monitoring) with local bus device id
   Dev_Adr_Monitor_IO = 0x15

   Address 0x000000 -> access to the supply voltage monitor
   Address 0x010000 -> access to the power bridge monitor



Firmware Release 716
====================

LK, 26.04.2010

Production Release

1) Analog Encoder Timing improvements
2) New Hardware support for prerelease TS Rev 2 "TSpreC"
3) The TSPreC has DSP parallel port interface included (test purposes)



Firmware Release 705
====================

LK, 06.04.2010

Production Release

1) Endat change (see last release) removed due to problems with the TIOB1
   Software implements a bugfix

   Default: Endat output signals deativated at startup.
 


Firmware Release 703
====================

LK, 09.03.2010

Production Release

1) TS Digital In with ram based digital inputs
 

   
Firmware Release 701
====================

LK, 12.01.2010

Production Release

1) Bug Fix Ram based Digital In (TIOB1)
2) Endat default settings changed to be backward compatible



Firmware Release 699
====================

LK, 06.01.2010

Do not use ...
Bugs when using ram based DigIn and Endat (wrong default)

1) Coefficient rOM bugfix (wrong rom entries)



Firmware Release 696
====================

LK, 16.12.2009

Buggy release ("Näggele" when using analog encoder at long distance moves)
Delivered by mistake !!!

1) TIOB1 full support with
   - 24 digital in
   - 8 digital out 
   - two encoders (digital encoder, pulse train)
   - 4 analog in (new device analog_in)
   - 4 analog out (new device analog_out)

2) Local Bus bug fixes (certain addresses returned wrong values)

3) Coefficient rOM redesign (unfortunately with wrong rom entries)



Firmware Release 683
====================

LK, 23.11.2009

Test-Version, upgrade NOT recommended due to 
changed motion control behaviour

1) New Current Filter Design
   Local Bus Address 0x000000-0x0003FF
   (Leading zeros in the coeffs removed)
2) New Position Filter Design
   Local Bus Address 0x000000-0x0003FF
   (Leading zeros in the coeffs removed)
3) Cordic based new ATAN calculation
4) TL and TLC with interrupt handler
   0x1100 [4:0] --> interrupt status
   0x1104 [4:0] --> interrupt mask
   0: rx asy fifo   '0' -> fifo empty, '1' -> fifo not empty
   1: rx iso fifo   '0' -> fifo empty, '1' -> fifo not empty
   2: tx asy fifo   '0' -> fifo full,  '1' -> fifo not full
   3: tx iso fifo   '0' -> fifo full,  '1' -> fifo not full
   4: sdram fifo    '0' -> fifo full,  '1' -> fifo not full
5) Hall counter included (connected to the didital counter 1)
   Device Encoder at 0x000040 bit 1 : '0' -> digital encoder source
                                      '1' -> hall signal source
   The hall signals are connected to extio 0-2.



Firmware Release 664
====================

LK, 09.09.2009

Test-Version, upgrade NOT recommended due to 
changed motion control behaviour

1) New Current Filter Design
   Local Bus Address 0x000000-0x0003FF
   (Include 4 leading zeros in the coeffs)
2) New Position Filter Design
   Local Bus Address 0x000000-0x0003FF
   (Include 8 leading zeros in the coeffs)
3) Cordic based new ATAN calculation
4) Longer Leica trigger pulse



Firmware Release 655
====================

LK, 10.07.2009

1) Extio 0&1 connected to cyclic data (digital in 6&7)
2) Leica trigger connected to Extio 3 instead of Extio 0



Firmware Release 654
====================

LK, 03.07.2009

1) Extio 0&1 connected to cyclic data (digital in 6&7)
2) Leica trigger connected to Extio 3 instead of Extio 0



Firmware Release 653
====================

LK, 25.06.2009

1) Integration of a PLL based external synchronisation with 1kHz sample rate 
   (used for Beckhoff SPS)
2) Base addresses of the point table fifos moved.
   sdram data fifo moved from 0x4000 to 0x7000
   sdram address fifo moved from 0x5000 to 0x6000 
   For SPS applications it is necessary to have the address fifo at a lower address
   than the data fifo (linear data copying).
3) Observer node address fixed to 253.
4) SPORT isochron receive synchronized to the 10kHz sampling rate. If more than 4 packets are
   in the fifo when sampling, the supernumerous packets will be flushed.
5) Increased PLL resolution implemented (100ppm instead of 1000ppm).



Firmware Release 641
====================

LK, 28.04.2009

production version (intensively tested)

1) TS15x, TS35x : Leica Encoder Interface integrated
2) TIOC : Testversion with trialink node
3) TLC100 HR2 : New implementation with new sdram size (256Mbit)
4) TL100, TLC201 HR1, TLC100 HR2 : Reset logic modifications (no software impact)
5) TL100, TLC201 HR1, TLC100 HR2 : external synching by the pci interface
   1200h [0] -> writing a '1' generates a synch trigger (10kHz)
   1204h [31:0] -> synch delay in 30ns steps (default = 0)
6) TL100, TLC201 HR1, TLC100 HR2 : variable fifo size
   value range is 1..63 packets
   value 0 means a fifo size of 63 (default)
   1008h   [5:0] -> rx asy fifo size 
   1008h  [13:8] -> rx iso fifo size
   1008h [21:16] -> tx asy fifo size 
   1008h [29:24] -> tx iso fifo size



Firmware Release 630
====================

LK, 30.01.2009

test version only

1) Pci interrupt connected (TL100 & TLC201) 
   Address 1008, bit 0
   '0' -> interrupt not active (default)
   '1' -> interrupt pending



Firmware Release 629
====================

LK, 10.12.2008

update strongly recommended

1) PLID is 2 which disables PulseTrain Utility 
2) Overall FPGA BuildProcess established
3) Drive bridge (LM73) overtemperature lowered from 80° to 70°
4) Drive electronics (ADT7476) overtemperature lowered from 70° to 65°



Firmware Release 627
====================

LK, 25.08.2008

update not recommended

1) PWM Test Mode bug fix with disable signal
2) Overcurrent debouncing from 200ns to 1us changed
3) Pulsetrain functionality
4) PLID 2 and 3 support



Firmware Release 595
====================

LK, 25.04.2008

update strongly recommended

Consolidating Version with
temperature measurement fixes for TS hardware fix B2



Firmware Release 582
====================

LK, 04.04.2008

update strongly recommended

1) I2c/SMB hardware bugfix

   The hardware monitoring reads the temperature and
   voltage converters via I2C lines. These lines are 
   opendrain driven with a fpga built-in pullup. The 
   high impedance lines are strongly disturbed when
   switching on the pwm unit (mainly with 350V drives).

   The following fix drives the clock and data lines 
   actively to the high signal level. I2C clock stretching
   is not further supported. When reading data, the bus will
   not be driven to the high level and, therefore reading data
   still will be noisy. The debouncing filter removes this
   input data noise and returns correct sensor data. a retry 
   furthermore algorithm increases the noise immunity. 

   When no data is available, the I2C controller will produce
   a overvoltage or overtemperature signal.

   The monitoring problem can't be solved with fpga changes only.
   The hardware fix "B2" is needed to improve I2C functionality.



Firmware Release 579
====================

LK, 01.04.2008

update not recommended

1) Temperature supervision is disabled because it is NOT possible
   to correct the I2C problems with the FPGA.

   The I2C inits a transmission start or stop when data changes
   while the clock line is high. When reading data from the devices,
   the data line is a relatively high ohm state and, therefore is
   sensitive against noise of the power stage. This results in erroneous
   data because of transmission interruption.

   The bug will be corrected by hardware change 
   (1k pullup resistor, 100p load capacitor). Eventually the lines to the LM73
   need to be disconnected.



Firmware Release 575
====================

LK, 28.03.2008

developper version

1) I2c/SMB hardware bugfix

   The hardware monitoring reads the temperature and
   voltage converters via I2C lines. These lines are 
   opendrain driven with a fpga built-in pullup. The 
   high impedance lines are strongly disturbed when
   switching on the pwm unit (mainly with 350V drives).

   The following fix drives the clock and data lines 
   actively to the high signal level. I2C clock stretching
   is not further supported. When reading data, the bus will
   not be driven to the high level and, therefore reading data
   still will be noisy. The debouncing filter removes this
   input data noise and returns correct sensor data. a retry 
   furthermore algorithm increases the noise immunity. 

   When no data is available, the I2C controller will produce
   a overvoltage or overtemperature signal.

   For test purposes the monitor device 0x06 returns the number of retries
   (bit2 23:16, values are 0, 1, 2, 3).

   When no data could be read, bit 24 will be set to one.



Firmware Release 557
====================

LK, 11.03.2008

BUG FIX DUe TO FIELD IMPUT
1) Debouncing of the over temperature and voltage signals (4 taps)



Firmware Release 553
====================

LK, 31.01.2008

1) FPGA internal : By optimizing the Fifo controller all 4 packets of the 
   available fifo memory can be used (instead of 3).



Firmware Release 552
====================

LK, 29.01.2008

1) TL100 Hardware with HR=0 will be no further supported.

2) Observer functionality (PCI-Bus only) integrated
   PCI-Register 0x1004 Bit 0 : 0 -> Master, 1 -> Observer

   Note, that a special link boot software is required when using an 
   observer in the ring.

   This feature is backward compatible (default is master)

3) FPGA internal : the fifo depth of status and control was reduced 
   from 31 to 3 packets. The goal of this change is to save 2 block
   rams per trialink node and allows in future to place 3 trialink nodes
   on a TLC201 board (required for USB support).

4) Pci Registers 0x1100-0x110C are connected to a SPI controller unit. 
   This allows programming the flash rom on a TL100 board over the PCI bus, 
   which is a requirement to upgrage Firmware of TL100 boards.

   0x1100 RW : DTR   Data Transmit Register
   0x1104 RO : DRR   Data Receive Register	
   0x1108 RW : CR    Control Register	
   0x110C RO : SR    Status Register
   
   Data Transmit Register (DTR)
   =============================
   The DTR holds the data to be transmitted in the next transfer. Valid
   bits depend on the DL field in the CR. DL = 7 means 8 bits, 31 means 32 bits an so on.
   	
   Data Receive Register (DRRx)
   ============================
   The DRR holds the value of received data of the last executed transfer. Valid
   bits depend on the DL field in the CR. DL = 7 means 8 bits, 31 means 32 bits an so on.
   
   Control Register (CR)
   =====================             																			
   [0]     EN   Enable               Enables the SPI unit. When disabled, the hardware outputs are set to tristate
   [1]     STA  Start Transmission   0 to 1 transition starts the next transmission. STA must remain 1 until SR sets TD to 1
   [2]     LSBF LSB First            0 -> MSB first, 1 -> LSB first
   [3]     CPOL Clock Polarity       Explanation see below
   [4]     CPHA Clock Phase          Explanation see below	
   [5]     CS   Chip Select          Level of chip select signal (without inversion)
   [12:8]  DL   Data Len             Number of bits = DL+1 to transmit/receive
   [31:16] CD   Clock Divider        Fsck = 33.33MHz / (CD + 1) / 2
		 																				 
   [CPOL = 0, CPHA = 0]              clock starts with rising  edge, new data at falling edge
   [CPOL = 0, CPHA = 1]              clock starts with rising  edge, new data at rising  edge
   [CPOL = 1, CPHA = 0]              clock starts with falling edge, new data at falling edge
   [CPOL = 1, CPHA = 1]              clock starts with falling edge, new data at rising  edge
   
   Status Register (SR)
   ====================
   [0]     TD   Transmission Done    After transmission completed, TD goes from 0 to 1 and remains 1 until STA is set to 0




Firmware Release 550
====================

LK, 17.01.2008

Upgrade strongly recommended for TS350
not recommended for TL* die to reset error

BUG FIXES
1) Refactoring of the SMB/I2C Bus
2) Local Bus access bug when reading the LM73 is solved
3) Bug with the ADT7476A Temperature Sensor (not active) solved




Firmware Release 546
====================

LK, 21.12.2007

Upgrade strongly recommended

BUG FIXES
1) Temperature monitoring activated for all 4 Sensors

KNOWN BUGS
1) Local bus access to the LM73 disturbs the temperature supervision




Firmware Release 532
====================

LK, 24.08.2007

Upgrade strongly recommended

BUG FIXES
1) Monitor interrupts disabled due to noise problems

FEATURES
1) Modified Encoder Device Register (enc_shift, 0x31, 7:3)




Firmware Release 529
====================

LK, 22.08.2007

Upgrade strongly recommended

BUG FIXES
1) Monitor Bug fix (auto start did not work)
2) Auto replace of slave sender node address to omit
   sending of packets with wrong sender address
3) ts150_ts350 mdio with pullup --> avoids unpredictable
   trialink communication loss

FEATURES
1) New Encoder Device Register (enc_shift, 0x31, 7:4)
2) scalable position (shift left by 0-15 bit) 




Firmware Release 527
====================

LK, 13.07.2007

First released 0x02xx firmware
including new local bus concept and endat 
 


   



   

   