Build 1.15.0
=====================

			TLO_500:
			Release for new hardware revision.
			New hardware has reset_n on M15 pin and pull up on B9.
			TlO500 Firmware tracks level on pin B9.
			If pin B9 = '0' then internal reset procedure
			If pin B9 = '1' then reset according to M15 pin
			


Build 1.13.9
=====================

			TOA3 change interpolation filter from 10 to 100 kHz

Build 1.12.9
=====================

			BugFix of 1.12.8:
			Remove subresolution from digital Position in Analog_Encoder_Counter:
				
			from :
				count_int <= cnt & quad_digital_old & digital_sub_res;
			to:
				count_int <= cnt & quad_digital_old & x"0000";


Build 1.12.8
=====================


			Ethercat		pll register in ethercat core available trough both local bus interfaces

Build 1.12.6
=====================

			Ethercat		repare DMA ethercat clock not connected


Build 1.12.5
=====================


			Trialink		Local_Bus_A53 Master is now single channel

Build 1.12.4
=====================

			Encoder		Some sources were not included correctly in 1.12.3


Build 1.12.3
=====================


			Trialink		Remove unused A53 interfaces	

Build 1.12.2
=====================

			Trialink		Remove Status _Control and implement new Trialink routing	
			
Build 1.12.1-proto
=====================

	
			New Encoder_Interface and digital encoder

Build 1.12.0-proto
=====================
	
			Backup for Synch with ladi


Build 1.11.34
=====================

			TLO500		Xilinx example project as base. no reset but 500 ms delay


Build 1.11.24
=====================

			TLO500 
					Base builds the Xilinx example project
					With sys_rst_n and quad spi (40 Mhz)

Build 1.11.23
=====================

			TLO500 
					Base builds the Xilinx example project
					No bitfile settings in tcl file	


Build 1.11.20
=====================

	Optionmodules with boot history


Build 1.11.17
=====================

	1.11.8-proto		TLO500 
					Reset 10 us, reset of pcie core does not affect USB node -> update should be possible			
					
	1.11.9-proto		TLO500 
					Memory log should not reset		
					
	1.11.10-proto		TLO500 
					ADD completion timeout state to pcie_controller
					Activate State logger

	1.11.11-proto		TLO500 
					Memory interface in pcie_contoller correct reset	

	1.11.12-proto		TLO500 
					State Logger stops after 1024 logs
		
	1.11.16-proto		TLO500 
					Memory logger in pcie clock domain but sensitive to reset.
					Warm_Reset counter in LB dev 0x17 reg 0x1
					State_logger with:
					user_lnk_up, pcie_reset, warm_reset, s_axi.tx_ready
	
	1.11.17		TLO500 
					state_logger sensitive to s_axi.tx_ready


Build 1.11.5
=====================

			PWM		separate sto shutdown from overcurrent shutdown

	
Build 1.11.4
=====================

			Common		ADD TSP700-15 to ident (0x014A)


Build 1.11.3
=====================

			PWM		OC high side and low side correct mapping to cyclic arm interface


Build 1.11.2
=====================
			Current		connect Dynamic config in generate axis loop



Build 1.11.2
=====================

			Current		Dynamic config is now:
					dyn_cfg.product_flags(0)    if 0  => overcurrent on dc bus is sigma delta else => comparator
					dyn_cfg.product_flags(1)    if 0  => phase u is measured else signed16_clear
					dyn_cfg.product_flags(2)    if 0  => phase v is measured else signed16_clear
					dyn_cfg.product_flags(3)    if 0  => phase w is measured else signed16_clear				


Build 1.11.0
=====================

			Encoder		analog - warning and error range were to large by factor 2				


Build 1.10.63
=====================

			TLO500 
					Changes in SDRAM controller, tablefeeder pointer was one bit short
					Pcie_controller changes to conform PCIE 2.1						


Build 1.10.61
=====================

			TSP700
					with correct measured behave (phase w is not measured in tsd 80)


Build 1.10.60
=====================

			TSP700
					correct filter parameter for current filter


Build 1.10.55
=====================

1.10.50-Beta	TLO500 
					with ASPM = false
					no wake capability
					
					
1.10.51			TLO500 
					add NEF_DEBUG_VECTOR to üpcie src, in vivado_script bypass pcie_core build
					
1.10.52			TLO500 
					log all signals in NEF_DEBUG_VECTOR
					
1.10.53			TLO500 
					repaired state logger, we was allways enabled
					
1.10.54			TLO500 
					remove NEF_DEBUG_VECTOR, add buf_av in scope
					
1.10.55			TLO500 
					Release Version without debug (except mem_logger)


Build 1.10.50-beta
=====================

1.10.39			TLO500 
					PCIE debugger longer logging after write access
			
1.10.39-Alpha	TLO500 
					PCIE debugger repair to long logging(1000 to 500) from 1.10.39
					
1.10.41			TLO500 
					Some PC used tags greater than 31 although its disabled in the core
					Incomming tags are now supported up to 255

1.10.42			TLO500 
					add state_logger with index 8
					in scope: track dstatus and buf_av

1.10.43			TLO500 
					restart capability for scope
					
					
1.10.44			TLO500 
					requests hot_reset after stuck in tx_H10 state for 50 ms
					
1.10.45			TLO500 
					remove hot_reset request
					
1.10.46			TLO500 
					add warm_reset on 0x1000 [1]

1.10.47			TLO500 
					wake on capability lb address 0x0 write	 0x1 (pcie_nsl_core build: option D3hot_PME_Support = true)

1.10.48			TLO500 
					1.10.47 with ASPM = true

1.10.50-Beta	TLO500 
					with ASPM = false
					no wake capability


Build 1.10.38-proto
=====================

1.10.16			TSP700 add ADC to curr_data(OC)

1.10.17			add DMA and MEM logging

1.10.19			TSP700
					all(u,v,w,oc) regardless of measured or not are routed to pwm unit
					lb_reg_pwm select bit is now routed to reset max/min
					new read register (20) for max/min
					dynamic_config is ignored in pwm unit
					curr_register debug enabled
					
1.10.20			TSP700
					dynamic_config is hot
					pwm_status.overcurrent_ls and pwm_status.overcurrent_hs controlled by dynamic_config
					
1.10.22			TSP700
					dynamic_config affects evaluation of oc on different bridges		
					
1.10.23			TLO500 
					add state_logger
					
1.10.24			TLO500 
					add pcie_ident and simple turn_of	
					
1.10.25			TSP700 
					overcurrent to arm false if adc oc	
					
1.10.26			TLO500 
					add state_logger with timestamp	
					
1.10.27			TSP700 
					overcurrent only on curr_0 when tsp700-10				
					
1.10.28			TLO500 
					force d0 on restart	does not work		
					
1.10.29			TLO500 
					reflash fpga when stuck on reboot pc				

1.10.33			TLO500 
					add 2 us reset delay for PCIE core		
					
1.10.34			TLO500 
					sync stat connected to table feeder		
					
1.10.35			TSP700 
					U_0 and OC_0 interchanged
			
1.10.36			TLO500 
					Very long PCIE RESET psoido hot plug (DOES NOT WORK)
					
1.10.37			TLO500 
					Very long PCIE RESET psoido hot plug

1.10.38			TLO500 
					add scope debugger
					disable user_access_value 0x5ff from .tcl


Build 1.10.15-proto
=====================
NEW BEGIN WITH BACKUP 1.9.0

1.10.0  (1.9.0) with:
			tx_dma only one at once (pcie_transaction, max_pending = 0 , copy statement)
			PCIE_NSL
				
1.10.1			dma_full = pending >= Max_Pending) 

1.10.2			flow_2 :
				pcie_controller requester, flow diag, pcie_config
				
1.10.3			FLOW_2 :
				pcie_transmit add pcie_identification
				
1.10.4			TLO_top :
				new master wrapper			
				
1.10.5			RESET :
				new reset behav
				
1.10.6			debug: registered hot reset, periphery reset on lpm
1.10.7			debug: only led affected on lpm
1.10.8			hot reset request on restart //Funktioniert nicht, warscheindlich wegen link down
1.10.9			Reboot
1.10.10			TLP_LOG
1.10.11			improved TLP_LOG
1.10.12			improved TLP_LOG
1.10.13			improved TLP_LOG (block_mem no reg)
1.10.14			improved TLP_LOG correct init
1.10.15			improved TLP_LOG cump one address when last


Build 1.10.1-proto
=====================

1.9.0  ACT	1.8.64 PCIE_A7 mit mehreren Architekturen (rtl und no shared logic(nsl)) aktiv = nsl (Läuft) 
1.9.1  MIT	1.9.0 pl_upstream_prefer_deemph                  => '0'  ,	 --1
1.9.1  MIT	1.9.0 pl_upstream_prefer_deemph                  => '1'
1.9.2  ACT	1.9.0 DDR_fifo_synch synch_when_change => true
1.9.3  ACT	Mit debug memory in DDR2_FLOW (debug unit funktioniert es scheint ein Fehler in der SDRAM clock domain crossing fifo zu sein)
1.9.4  ACT	Mit seperate head and tail in sdram fifo bus write sdram_fifo_bus_write(debug)	kein Einfluss
1.9.5  ACT	Mit ddr2_cdc 					kein Einfluss
1.9.6  1.9.2 Mit debug memory in DDR2_FLOW und LED FREQ DETECTION
1.9.7  1.9.2 Mit debug memory in DDR2_FLOW und LED FREQ DETECTION on user_clk
1.9.8  1.9.2 Flow control with extended sdram address range
1.9.9  1.9.2 Flow control normal and different memory map
1.9.10	keine debugg utilitys, memory map control register mit reset
1.9.11	debugg in ddr2_Flow + Cyclic interrupt
1.9.12	fifo asynchron sdram arch = debugg, tail in log unit
1.9.13	max one dma pending
1.9.14	debug in sdram wifo write
1.9.15	in fifo_diag
1.9.16	interrupt on dma sensitive
1.9.17	Advanced Reset concept
1.9.18	Reset Master or verknüpft mit soft reset/ usb reset 5s
1.9.19	DMA MAX Pending 1
1.9.20	fifo asynchron sdram arch = debugg, tail in log unit
1.9.21	in transaction read dma nur wenn nicht pending
1.9.22	sa und sd waren vertauscht usb reset nicht über softreset
1.9.23	pcie power setting disabled, phy reset trialink, Observer disabled / 66MHz spi flash
1.9.26	ASPM_Optionality
1.9.27	no ASPM_Optionality / lpm / requester in pcie_controller
1.9.28	new layout and new reset !!!!!!!FEHLER DRIN DMA FUNKTIONIERT NICHT MEHR
1.9.29	revert: pcie_controller requester, trialink_master
1.9.30	revert: pll
1.9.31	add generics
1.9.32	correct resets on ddr unit

NEW BEGIN WITH BACKUP 1.9.0




Build 1.8.0-proto
=====================

1.8.50 MIT NSL CORE
1.8.51 MIT 1.8.7 IMAGE DDR2_CTRL_2
1.8.52 ACT	MIT ALTEM CORE und DDR2_CTRL_2
1.8.53 MIT 1.8.7 IMAGE und angepasstem ident register und DDR2_CTRL_2
1.8.54 ACT	1.8.7 und MIT ALTEM PCIE_SUPPORT/PCIE_A7
1.8.55 MIT 1.8.7 IMAGE und angepasstem ident register und DDR2_CTRL_2 + NEUES CONSTTRAINTS FILE
1.8.56 ACT	build 1.8.54 mit ddr2_flow_fast
1.8.57 ACT	build 1.8.54 mit ddr2_flow_fast mit configuration(fast)
1.8.58 ACT	1.8.54 angepasstem USB RESET 
1.8.59 ACT 	With user_access_reg
1.8.60 ACT 	With user_access_reg to pcie_config 24 bit
1.8.61 ACT 	With user_access_reg to pcie_config 32 bit /constainr 502 serial number / qspi io buff
1.8.62 ACT 	(Falscher RESET)1.8.61 mit korrigierter status LED und zusätzliche timing constraints
1.8.63 ACT 	(Falscher RESET)1.8.61 mit korrigierter status LED und alte timing constraints
1.8.64 ACT 	1.8.63 mit korrigierter Reset und PCIE in project build (IP GEN CONSTRAINTS) (Läuft)



--TLO500 PCIE CORE nsl

-- Analog Position_Filter, change latch prio in sequ process
-- add quadrant error to incremental encoder
-- TLO/USB if_clk change ibufg to ibuf
-- tlo constraints correct path
-- remove constraints that belongs to the ddr core
-- set encoder autocalib to RTL full
-- TLO 500 correct md_data port, TCL add pullup & pulldown rx_d[]
-- TLO500 change refclock to 200Mhz for idelay
-- TLO500 in pcie_controller correct read length
-- Trialink: in Status_Controll_Fifo change source address allways own node address
-- Trialink: in pll_state_machine change reset condition
-- Encoder enc_latch_source_reg_mask is now 0x00070107 but was 0x00030107
-- Trialink Fifo_Synch_multiple revert to old source
-- ENDAT ERROR 2 logic inverted
-- TLO_FLASHER qspi 0 and qspi 1 (miso mosi) change to IOBUF
-- USB reset improfment

Build 1.8.6
=====================

	add dynamic config to the ident register
Current_Unitr:
	the current adc timing depens now on the product_id field in the dynamic config

Build 1.8.4
=====================
TOF2		:	  add config to slave_top


Build 1.8.3
=====================

ENCODER 	:	-add analog_error and analog_warning to position_status_type
				 enc_error_2 and enc_error_1 are now serial encoder flags
				 analog_error and analog_warning only for analog encoder
				
				-in analog_enc_counter correct warn and error range 				
				
				- analog_error, analog_warning, encoder_error, encoder_warning 10kHz latched



Build 1.8.2
=====================

ENCODER 	:	new aligment cyclic data
				repair error and warning hysteresis filter coef
				AD9822 Saturation
				Error and warning filter to 8 bit width
				
Current		:	default values for current measurement timing (tsd80, tsd350, tsp700)
TOE1		:	new aligment cyclic data 
TOE2 		:	new aligment cyclic data 
				set EXT_IO to 'Z'
TOF2		:	add new mode timed pulse
				pins enc_ext_io, tx_rx_clk, tx_rx_z drive '0' if enable is not set


Build 1.7.26
=====================

Add timing analysis to current adc
add x_range and y_range to encoder and cyclic data


Build 1.6.9 -BUGFIX
=====================

BUG FIX AD9822 Saturation.


Build 1.7.10
=====================

VCXO bug fix


Build 1.7.9
=====================

TSP700-300:
multiple bridges added


Build 1.6.12
=====================

TOA3 Build with release bit file


Build 1.6.9
=====================

TOA3 with non interruptive asynchron register read
TOE1 & TOE2 possition error_1 was not mapped in cyclic data


Build 1.6.7-proto
=====================

Add TOA3


Build 1.5.11
=====================

TOA4 SPI slow clock duration was 10 but should be 12


Build 1.5.10
=====================

TOA4 with internal oversampling


Build 1.5.9
=====================

Transistor test shutdown changes


Build 1.5.6
=====================

Fix Transistor Test Mode in PWM Unit


Build 1.5.5
=====================

Add available register to monitors (0x4400)
Repair debounce time in overcurrent detection 


Build 1.5.4
=====================

add Monitors (8 to 32)


Build 1.5.0-beta
=====================

New PWM Unit


Build 1.4.15
=====================

Add Pwm Transistor Test


Build 1.4.12-proto
=====================

can be deleted is for test 


Build 1.4.12-proto
=====================

test for bitfile can be deleted


Build 1.4.11
=====================

Repair enable signals for every transistor in PWM unit


Build 1.4.9
=====================

PWM_Distribution unit immediately transfers shutdown and enable


Build 1.4.8
=====================

Add Enable signals to PWM Unit.
PWM Shutdown is now 100kHz


Build 1.4.7.release
=====================

Add PWM_Merge


Build 1.4.6.release
=====================

TSP700 : FPGA PIN 57 to 61
add edge detect for incr signal in fifo_synch_multiple_large  


Build 1.4.5
=====================

Repair Trialink Fifos


Build 1.4.4
=====================

new bitfile name


Build 1.4.4.release
=====================

add Trialink watchdog timer
double size trialink fifo
add lsb timestamp to extio


Build 1.4.4.proto
=====================

TOA4 PROTO


Build 1.4.3.release
=====================

PWM unit repared 2 Level Drives are now connected to upper_middle and lower_middle

Build 1.4.2.proto
=====================

PWM Mode_0 for 2 Level devices and Mode_2 for 3_Level devices


Build 1.4.0.release
=====================

New release with 3 level PWM , serial encoder with comm_error, and 3  phase current


Build 1.3.12.release
=====================

Current U,V,W with 18 bit resolution


Build 1.3.11.release
=====================
3 Level PWM Unit
Serial Encoder (except Endat) with comunication error and valid flag(OPT MODULES)



Build 1.3.11.release
=====================

3 Level PWM Unit
Serial Encoder (except Endat) with comunication error and valid flag




Build 1.3.10.beta
=====================

3 Level PWM Mit getesteter PWM UNIT


Build 1.3.10.beta
=====================

3 Level PWM Test 




Build 1.3.9.release
=====================

FN,  28.01.2020
CHG: In file : 	TamservoDue\OptionModules\src\Slave\Slave_Top.vhd

		Add Boot_Control and A7_Health_Monitor to slave_top.vhd


Build 1.3.8.release
=====================

FN,  20.01.2020
CHG: In file : 	TamservoDue\toe1\src\Encoder\IO_Interface.vhd
	       	TamservoDue\Build\src\TS\tsd80_port_driver.vhd
		TamservoDue\Build\src\TS\tsd350_port_driver.vhd
		TamservoDue\Build\src\TS\tsd710_port_driver.vhd

		in all Files add a pulldown resistor to the encoder ext_io


Build 1.3.7.release
=====================

FN,  12.12.2019
CHG: In file : TamservoDue\toe1\src\Encoder\IO_Interface.vhd
     tri state selector from IOBUF(enc_ext_io) was inverted.
     enc_out.tri is default '1' therefore tristate selector must not be inverted



FN,  08.11.2019
CHG: In file : TamservoDue\OptionModules\src\Common\Option_Definitions.vhd
     Change read mask for Firmware ident from 0xFFFF to 0xFFFFFF
CHG: In file : TamservoDue\Build\src\Scripts_Common\Backup.tcl   
     Bit File Format from TOE1_FF1.3.6_HC03_PL4.bit to TOE1-HC3-1.3.6-PL4.bit

FN,  05.11.2019
CHG: In file : TamServoDue\Encoder\src\Analog\Ad9822_Conv.vhd   
     Changes from 1.3.5 to 1.3.6 were malformed and now correct


FN,  04.11.2019
CHG: In file : TamservoDue\Build\src\Scripts_Common\Backup.tcl   
     Bit File Format from toe1_hc3_1.3.6.bit to TOE1_FF1.3.6_HC03_PL4.bit


Build 1.3.6.release
=====================

FN,  28.10.2019

CHG: In file : TamServoDue\Encoder\src\Analog\Ad9822_Conv.vhd    
     saturation for enc_int.x and enc_int.y


Build 1.3.5.release
===================

LK, 20.09.2019

CHG: endat position with sign extension



Build 1.3.4.release
===================

LK, 28.08.2019

CHG: Build with Vivado 2018.2
FIX: Global latch digital input inverted



Build 1.3.3-release
===================

LK, 10.07.2019

FIX: software controlled switch on of the TAD SPI DRIVERS. If an option module is connected, CS_N and SCLK must be kept tristate to avoid a short between the spi outputs and the safety encoder outputs. 

Local bus devices 0x80, 0x81, 0xA0, 0xA1

RESET CONTROL
0x000010 RW [ 1]    delay reset            default '0'
            [ 2]    delay control reset    default '0'
            [ 3]    receiver reset         default '0'
            [ 4]    sender reset           default '0'
            [ 5]    cyclic                 default '0'
            [ 6]    auto calib             default '1'
            [ 8]    enable tad module      default '0'	
                    switch on only if there is no option module.
                    this would lead to a short of the drivers.



Build 1.3.2-release
===================

LK, 01.07.2019

NEW: Node addresses can be changed by local bus
NEW: Dedicated node addresses for bridge mode by USB or Ethernet over a drive.
NEW: drive can overtake the trialink master role (rings without trialink controller card)



Build 1.2.11-release
====================

LK, 06.02.2019

FIX: option modules transmit data with a downsampling of 79 due to a bug
     inside the new Zynq SERDES calibration unit.

NEW: first TSP710 support with 2-Level Pwm
NEW: Nikon encoder support
NEW: Tamagawa encoder support
NEW: Extended encoder error messages (not yet completed)
CHG: Serial encoder rework
NEW: Serial encoder without bit filter
FIX: Pll error counters were not clearable



Build 1.1.11-release
====================

LK, 18.1.2019

FIX: option modules transmit data with a downsampling of 79 due to a bug
     inside the new Zynq SERDES calibration unit.




Build 1.1.10-release
====================

DO NOT USE

LK, 14.1.2019

CHG: analog pll oscillator removed
CHG: old position fir filter removed
CHG: encoder amplitude error and warning passed through a bit filter
CHG: encoder amplitude error mapped to encoder error 1
CHG: encoder amplitude warning mapped to encoder error 2
NEW: encoder error handling
NEW: biss b, biss c and ssi encoder
CHG: endat local bus rework
NEW: encoder error signals on cyclic interface
CHG: pll not locked behaviour (debouncing of the errors)



Build 1.1.4-release
===================

LK, 12.11.2018

CHG: local bus interface to the endat unit (biss encoder preparation work)
NEW: biss encoder (do not use yet)



Build 1.1.0-proto
=================

LK, 09.11.2018

NEW: BISS B / BISS C / SSI support

NEW: pLL plot signals using encoder phase A and B

     encoder device, Address 0x40 [19:16]
       0x0 => uncalibrated encoder phase A
       0x1 => calibrated encoder phase B
       0x2 => encoder phase A offset C1
       0x3 => encoder phase A amplitude A11
       0x4 => encoder phase A cross-amplitude A12
       0x8 => pll phase error
       0x9 => pll phase count of ring 1
       0xA => ethernet intermediate gap length of ring 1
       0xB => ethernet frame length of ring 1

     encoder device, Address 0x40 [23:20]
       0x0 => uncalibrated encoder phase B
       0x1 => calibrated encoder phase A
       0x2 => encoder phase B offset C2
       0x3 => encoder phase B amplitude A22
       0x4 => encoder phase B cross-amplitude A21
       0x8 => pll frequency
       0x9 => pll phase count of ring 2
       0xA => ethernet intermediate gap length of ring 2
       0xB => ethernet frame length of ring 2

CHG: ethernet frame tolerance set to +/-160ns
CHG: ethernet gap tolerance set to +/-320ns
CHG: timestamp crc error counted as a packet crc error
CHG: frame error, gap error and crc error of packets counted once every 100us
CHG: physical link device, see local bus description

FIX: pll not locked error when one timestamp with crc error occurs. this throws an error
     to the drive stopping the motion. Changed to pll not locked error when multiple 
     timestamp with crc error occurs. "multiple" is programmable from 1 to 128 with 
     default of 32.

FIX: crc calculation of ethernet rx and tx divided into two calculation steps to avoid
     wrong crc calculation when fpga device gets hot.



Build 1.0.10-alpha
==================

LK, 25.06.2018

CHG: Option module auto calibration measuring both lanes to find optimal eye position 



Build 1.0.9-alpha
=================

LK, 22.06.2018

NEW: First Zynq release based on Artix-7
NEW: Access to the factory by AXI-Bus
CHG: Option module modifications due to new delay and serdes unit
CHG: Pwm fine resolution with new serdes
CHG: Current measurement with serdes instead of ddr register
CHG: PLL with digital oscillator and inverted sign
CHG: Current measurement with different sign (inverted clock driver)
CHG: Current sampling at different position in order to correct the delay of the clock driver

Generally many many little changes...

Supported devices:

TSD80130T
TSD80130E
TSD350T
TSD350E