Build 1.8.54
=====================

TLO_500 Release

Build 1.8.6
=====================

	add dynamic config to the ident register
Current_Unitr:
	the current adc timing depens now on the product_id field in the dynamic config

Build 1.8.4
=====================
TOF2		:	  add config to slave_top


Build 1.8.3
=====================

ENCODER 	:	-add analog_error and analog_warning to position_status_type
				 enc_error_2 and enc_error_1 are now serial encoder flags
				 analog_error and analog_warning only for analog encoder
				
				-in analog_enc_counter correct warn and error range 				
				
				- analog_error, analog_warning, encoder_error, encoder_warning 10kHz latched



Build 1.8.2
=====================

ENCODER 	:	new aligment cyclic data
				repair error and warning hysteresis filter coef
				AD9822 Saturation
				Error and warning filter to 8 bit width
				
Current		:	default values for current measurement timing (tsd80, tsd350, tsp700)
TOE1		:	new aligment cyclic data 
TOE2 		:	new aligment cyclic data 
				set EXT_IO to 'Z'
TOF2		:	add new mode timed pulse
				pins enc_ext_io, tx_rx_clk, tx_rx_z drive '0' if enable is not set


Build 1.7.26
=====================

Add timing analysis to current adc
add x_range and y_range to encoder and cyclic data


Build 1.6.9 -BUGFIX
=====================

BUG FIX AD9822 Saturation.


Build 1.7.10
=====================

VCXO bug fix


Build 1.7.9
=====================

TSP700-300:
multiple bridges added


Build 1.6.12
=====================

TOA3 Build with release bit file


Build 1.6.9
=====================

TOA3 with non interruptive asynchron register read
TOE1 & TOE2 possition error_1 was not mapped in cyclic data


Build 1.6.7-proto
=====================

Add TOA3


Build 1.5.11
=====================

TOA4 SPI slow clock duration was 10 but should be 12


Build 1.5.10
=====================

TOA4 with internal oversampling


Build 1.5.9
=====================

Transistor test shutdown changes


Build 1.5.6
=====================

Fix Transistor Test Mode in PWM Unit


Build 1.5.5
=====================

Add available register to monitors (0x4400)
Repair debounce time in overcurrent detection 


Build 1.5.4
=====================

add Monitors (8 to 32)


Build 1.5.0-beta
=====================

New PWM Unit


Build 1.4.15
=====================

Add Pwm Transistor Test


Build 1.4.12-proto
=====================

can be deleted is for test 


Build 1.4.12-proto
=====================

test for bitfile can be deleted


Build 1.4.11
=====================

Repair enable signals for every transistor in PWM unit


Build 1.4.9
=====================

PWM_Distribution unit immediately transfers shutdown and enable


Build 1.4.8
=====================

Add Enable signals to PWM Unit.
PWM Shutdown is now 100kHz


Build 1.4.7.release
=====================

Add PWM_Merge


Build 1.4.6.release
=====================

TSP700 : FPGA PIN 57 to 61
add edge detect for incr signal in fifo_synch_multiple_large  


Build 1.4.5
=====================

Repair Trialink Fifos


Build 1.4.4
=====================

new bitfile name


Build 1.4.4.release
=====================

add Trialink watchdog timer
double size trialink fifo
add lsb timestamp to extio


Build 1.4.4.proto
=====================

TOA4 PROTO


Build 1.4.3.release
=====================

PWM unit repared 2 Level Drives are now connected to upper_middle and lower_middle

Build 1.4.2.proto
=====================

PWM Mode_0 for 2 Level devices and Mode_2 for 3_Level devices


Build 1.4.0.release
=====================

New release with 3 level PWM , serial encoder with comm_error, and 3  phase current


Build 1.3.12.release
=====================

Current U,V,W with 18 bit resolution


Build 1.3.11.release
=====================
3 Level PWM Unit
Serial Encoder (except Endat) with comunication error and valid flag(OPT MODULES)



Build 1.3.11.release
=====================

3 Level PWM Unit
Serial Encoder (except Endat) with comunication error and valid flag




Build 1.3.10.beta
=====================

3 Level PWM Mit getesteter PWM UNIT


Build 1.3.10.beta
=====================

3 Level PWM Test 




Build 1.3.9.release
=====================

FN,  28.01.2020
CHG: In file : 	TamservoDue\OptionModules\src\Slave\Slave_Top.vhd

		Add Boot_Control and A7_Health_Monitor to slave_top.vhd


Build 1.3.8.release
=====================

FN,  20.01.2020
CHG: In file : 	TamservoDue\toe1\src\Encoder\IO_Interface.vhd
	       	TamservoDue\Build\src\TS\tsd80_port_driver.vhd
		TamservoDue\Build\src\TS\tsd350_port_driver.vhd
		TamservoDue\Build\src\TS\tsd710_port_driver.vhd

		in all Files add a pulldown resistor to the encoder ext_io


Build 1.3.7.release
=====================

FN,  12.12.2019
CHG: In file : TamservoDue\toe1\src\Encoder\IO_Interface.vhd
     tri state selector from IOBUF(enc_ext_io) was inverted.
     enc_out.tri is default '1' therefore tristate selector must not be inverted



FN,  08.11.2019
CHG: In file : TamservoDue\OptionModules\src\Common\Option_Definitions.vhd
     Change read mask for Firmware ident from 0xFFFF to 0xFFFFFF
CHG: In file : TamservoDue\Build\src\Scripts_Common\Backup.tcl   
     Bit File Format from TOE1_FF1.3.6_HC03_PL4.bit to TOE1-HC3-1.3.6-PL4.bit

FN,  05.11.2019
CHG: In file : TamServoDue\Encoder\src\Analog\Ad9822_Conv.vhd   
     Changes from 1.3.5 to 1.3.6 were malformed and now correct


FN,  04.11.2019
CHG: In file : TamservoDue\Build\src\Scripts_Common\Backup.tcl   
     Bit File Format from toe1_hc3_1.3.6.bit to TOE1_FF1.3.6_HC03_PL4.bit


Build 1.3.6.release
=====================

FN,  28.10.2019

CHG: In file : TamServoDue\Encoder\src\Analog\Ad9822_Conv.vhd    
     saturation for enc_int.x and enc_int.y


Build 1.3.5.release
===================

LK, 20.09.2019

CHG: endat position with sign extension



Build 1.3.4.release
===================

LK, 28.08.2019

CHG: Build with Vivado 2018.2
FIX: Global latch digital input inverted



Build 1.3.3-release
===================

LK, 10.07.2019

FIX: software controlled switch on of the TAD SPI DRIVERS. If an option module is connected, CS_N and SCLK must be kept tristate to avoid a short between the spi outputs and the safety encoder outputs. 

Local bus devices 0x80, 0x81, 0xA0, 0xA1

RESET CONTROL
0x000010 RW [ 1]    delay reset            default '0'
            [ 2]    delay control reset    default '0'
            [ 3]    receiver reset         default '0'
            [ 4]    sender reset           default '0'
            [ 5]    cyclic                 default '0'
            [ 6]    auto calib             default '1'
            [ 8]    enable tad module      default '0'	
                    switch on only if there is no option module.
                    this would lead to a short of the drivers.



Build 1.3.2-release
===================

LK, 01.07.2019

NEW: Node addresses can be changed by local bus
NEW: Dedicated node addresses for bridge mode by USB or Ethernet over a drive.
NEW: drive can overtake the trialink master role (rings without trialink controller card)



Build 1.2.11-release
====================

LK, 06.02.2019

FIX: option modules transmit data with a downsampling of 79 due to a bug
     inside the new Zynq SERDES calibration unit.

NEW: first TSP710 support with 2-Level Pwm
NEW: Nikon encoder support
NEW: Tamagawa encoder support
NEW: Extended encoder error messages (not yet completed)
CHG: Serial encoder rework
NEW: Serial encoder without bit filter
FIX: Pll error counters were not clearable



Build 1.1.11-release
====================

LK, 18.1.2019

FIX: option modules transmit data with a downsampling of 79 due to a bug
     inside the new Zynq SERDES calibration unit.




Build 1.1.10-release
====================

DO NOT USE

LK, 14.1.2019

CHG: analog pll oscillator removed
CHG: old position fir filter removed
CHG: encoder amplitude error and warning passed through a bit filter
CHG: encoder amplitude error mapped to encoder error 1
CHG: encoder amplitude warning mapped to encoder error 2
NEW: encoder error handling
NEW: biss b, biss c and ssi encoder
CHG: endat local bus rework
NEW: encoder error signals on cyclic interface
CHG: pll not locked behaviour (debouncing of the errors)



Build 1.1.4-release
===================

LK, 12.11.2018

CHG: local bus interface to the endat unit (biss encoder preparation work)
NEW: biss encoder (do not use yet)



Build 1.1.0-proto
=================

LK, 09.11.2018

NEW: BISS B / BISS C / SSI support

NEW: pLL plot signals using encoder phase A and B

     encoder device, Address 0x40 [19:16]
       0x0 => uncalibrated encoder phase A
       0x1 => calibrated encoder phase B
       0x2 => encoder phase A offset C1
       0x3 => encoder phase A amplitude A11
       0x4 => encoder phase A cross-amplitude A12
       0x8 => pll phase error
       0x9 => pll phase count of ring 1
       0xA => ethernet intermediate gap length of ring 1
       0xB => ethernet frame length of ring 1

     encoder device, Address 0x40 [23:20]
       0x0 => uncalibrated encoder phase B
       0x1 => calibrated encoder phase A
       0x2 => encoder phase B offset C2
       0x3 => encoder phase B amplitude A22
       0x4 => encoder phase B cross-amplitude A21
       0x8 => pll frequency
       0x9 => pll phase count of ring 2
       0xA => ethernet intermediate gap length of ring 2
       0xB => ethernet frame length of ring 2

CHG: ethernet frame tolerance set to +/-160ns
CHG: ethernet gap tolerance set to +/-320ns
CHG: timestamp crc error counted as a packet crc error
CHG: frame error, gap error and crc error of packets counted once every 100us
CHG: physical link device, see local bus description

FIX: pll not locked error when one timestamp with crc error occurs. this throws an error
     to the drive stopping the motion. Changed to pll not locked error when multiple 
     timestamp with crc error occurs. "multiple" is programmable from 1 to 128 with 
     default of 32.

FIX: crc calculation of ethernet rx and tx divided into two calculation steps to avoid
     wrong crc calculation when fpga device gets hot.



Build 1.0.10-alpha
==================

LK, 25.06.2018

CHG: Option module auto calibration measuring both lanes to find optimal eye position 



Build 1.0.9-alpha
=================

LK, 22.06.2018

NEW: First Zynq release based on Artix-7
NEW: Access to the factory by AXI-Bus
CHG: Option module modifications due to new delay and serdes unit
CHG: Pwm fine resolution with new serdes
CHG: Current measurement with serdes instead of ddr register
CHG: PLL with digital oscillator and inverted sign
CHG: Current measurement with different sign (inverted clock driver)
CHG: Current sampling at different position in order to correct the delay of the clock driver

Generally many many little changes...

Supported devices:

TSD80130T
TSD80130E
TSD350T
TSD350E