Build 1.3.5.release
===================

LK, 20.09.2019

CHG: endat position with sign extension




Build 1.3.4.release
===================

LK, 28.08.2019

CHG: Build with Vivado 2018.2
FIX: Global latch digital input inverted



Build 1.3.3-release
===================

LK, 10.07.2019

FIX: software controlled switch on of the TAD SPI DRIVERS. If an option module is connected, CS_N and SCLK must be kept tristate to avoid a short between the spi outputs and the safety encoder outputs. 

Local bus devices 0x80, 0x81, 0xA0, 0xA1

RESET CONTROL
0x000010 RW [ 1]    delay reset            default '0'
            [ 2]    delay control reset    default '0'
            [ 3]    receiver reset         default '0'
            [ 4]    sender reset           default '0'
            [ 5]    cyclic                 default '0'
            [ 6]    auto calib             default '1'
            [ 8]    enable tad module      default '0'	
                    switch on only if there is no option module.
                    this would lead to a short of the drivers.



Build 1.3.2-release
===================

LK, 01.07.2019

NEW: Node addresses can be changed by local bus
NEW: Dedicated node addresses for bridge mode by USB or Ethernet over a drive.
NEW: drive can overtake the trialink master role (rings without trialink controller card)



Build 1.2.11-release
====================

LK, 06.02.2019

FIX: option modules transmit data with a downsampling of 79 due to a bug
     inside the new Zynq SERDES calibration unit.

NEW: first TSP710 support with 2-Level Pwm
NEW: Nikon encoder support
NEW: Tamagawa encoder support
NEW: Extended encoder error messages (not yet completed)
CHG: Serial encoder rework
NEW: Serial encoder without bit filter
FIX: Pll error counters were not clearable



Build 1.1.11-release
====================

LK, 18.1.2019

FIX: option modules transmit data with a downsampling of 79 due to a bug
     inside the new Zynq SERDES calibration unit.




Build 1.1.10-release
====================

DO NOT USE

LK, 14.1.2019

CHG: analog pll oscillator removed
CHG: old position fir filter removed
CHG: encoder amplitude error and warning passed through a bit filter
CHG: encoder amplitude error mapped to encoder error 1
CHG: encoder amplitude warning mapped to encoder error 2
NEW: encoder error handling
NEW: biss b, biss c and ssi encoder
CHG: endat local bus rework
NEW: encoder error signals on cyclic interface
CHG: pll not locked behaviour (debouncing of the errors)



Build 1.1.4-release
===================

LK, 12.11.2018

CHG: local bus interface to the endat unit (biss encoder preparation work)
NEW: biss encoder (do not use yet)



Build 1.1.0-proto
=================

LK, 09.11.2018

NEW: BISS B / BISS C / SSI support

NEW: pLL plot signals using encoder phase A and B

     encoder device, Address 0x40 [19:16]
       0x0 => uncalibrated encoder phase A
       0x1 => calibrated encoder phase B
       0x2 => encoder phase A offset C1
       0x3 => encoder phase A amplitude A11
       0x4 => encoder phase A cross-amplitude A12
       0x8 => pll phase error
       0x9 => pll phase count of ring 1
       0xA => ethernet intermediate gap length of ring 1
       0xB => ethernet frame length of ring 1

     encoder device, Address 0x40 [23:20]
       0x0 => uncalibrated encoder phase B
       0x1 => calibrated encoder phase A
       0x2 => encoder phase B offset C2
       0x3 => encoder phase B amplitude A22
       0x4 => encoder phase B cross-amplitude A21
       0x8 => pll frequency
       0x9 => pll phase count of ring 2
       0xA => ethernet intermediate gap length of ring 2
       0xB => ethernet frame length of ring 2

CHG: ethernet frame tolerance set to +/-160ns
CHG: ethernet gap tolerance set to +/-320ns
CHG: timestamp crc error counted as a packet crc error
CHG: frame error, gap error and crc error of packets counted once every 100us
CHG: physical link device, see local bus description

FIX: pll not locked error when one timestamp with crc error occurs. this throws an error
     to the drive stopping the motion. Changed to pll not locked error when multiple 
     timestamp with crc error occurs. "multiple" is programmable from 1 to 128 with 
     default of 32.

FIX: crc calculation of ethernet rx and tx divided into two calculation steps to avoid
     wrong crc calculation when fpga device gets hot.



Build 1.0.10-alpha
==================

LK, 25.06.2018

CHG: Option module auto calibration measuring both lanes to find optimal eye position 



Build 1.0.9-alpha
=================

LK, 22.06.2018

NEW: First Zynq release based on Artix-7
NEW: Access to the factory by AXI-Bus
CHG: Option module modifications due to new delay and serdes unit
CHG: Pwm fine resolution with new serdes
CHG: Current measurement with serdes instead of ddr register
CHG: PLL with digital oscillator and inverted sign
CHG: Current measurement with different sign (inverted clock driver)
CHG: Current sampling at different position in order to correct the delay of the clock driver

Generally many many little changes...

Supported devices:

TSD80130T
TSD80130E
TSD350T
TSD350E